Typo in project assignment + information on the SAR logic_澳门皇冠体育,皇冠足球比分

dagwis
2021-04-19T10:35:00.233Z
type:structured-message
www.uio.no

There is a small typo in the DAC specifications; the resolution should be 8 bit and not 9 bit as written.

Also if you compare the I/O of the provided SAR logic it does not fully match the block diagram used in the project assignment. The SAR logic has the following signals:

Input signals:

clk: This is the clock for the SAR logic

soc: This is the Start-of-Conversion signal. It will reset the SAR logic to the starting state. Compared to the figure in the project assignment which has both reset and soc, this is combined in the SAR logic

keep: This signal monitors the output of the comparator and if it is inverted, the digital code is too high and one must revert back to the past state and move to a less significant bit.

Output signals:

dout: The eight bit digital output

done: Status signal telling the the bit cycling is completed and the conversion is done.
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